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Your search returned 19 records. Click on the hyperlinks to view further details of Titles.. |
Magazine Name : Ieee Transactions On Very Large Scale Intergration (Vlsi) Systems
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Year : 2000 Volume number : 08 Issue: 05 |
Synthesis For Logical Initializability Of Synchronous Finite-State Machines.
(Article)
Subject:
Automatic Test-Pettern Generation (Atpg)
,
Three-Value Simulation
Author:
M
Singh
S. M
Nowick
page:
242
-
557
11th International Symposium On System-Level Synthesis And Design (Isss'98).
(Article)
Subject:
Author:
N. D
Dutt
A. C. H
Wu
page:
469
-
471
Scheduling With Bus Access Optimization For Distributed Embedded Systems.
(Article)
Subject:
Real-Time Systems
,
Time-Triggered Protocol
Author:
P
Pop
A
Deboli
P
Eles
page:
472
-
491
Performance Improvement Of Geographically Distributed Cosimulation By Hierarchically Grouped Messages.
(Article)
Subject:
Simulation
,
Performance Roolback
Author:
S
Yoo
D. S
Ha
K
Choi
page:
492
-
502
Hierarchical System Test By An Ieee 11490.5 Mtm-Bus Slave-Module Interface Core.
(Article)
Subject:
Boundary Scan
,
System-On-Chip
Author:
J. H
Hong
C. H
Tsai
C. W
Wu
page:
503
-
516
Exact Memory Size Estimation For Array Computations.
(Article)
Subject:
Memory Size
,
Integer Point Counting
Author:
S
Malik
Y
Zhao
page:
517
-
521
Memory Efficient Software Synthesis With Mixed Coding Style From Dataflow Graphs.
(Article)
Subject:
Code Sharing
,
Schedule Adjustment
Author:
S
Ha
W
Sung
page:
522
-
525
A Compositional Model For The Functional Verification Of High-Level Synthesis Results.
(Article)
Subject:
Author:
D
Borrione
J
Dushina
L
Pierre
page:
526
-
529
Expression-Tree-Based Algorithms For Code Compression On Embedded Risc Architectures.
(Article)
Subject:
Code Compression
,
Risc Architecture
Author:
R
Pannain
R
Azevedo
P
Centoducatte
page:
530
-
533
Partitioning Sequential Circuits For Pseudoexhaustive Testing.
(Article)
Subject:
Digital Very Large Scale Integraion (Vlsi) Circuits
,
Fanout
Author:
D
Landis
S. A
Al-Arian
B
Shaer
page:
534
-
541
Threshold Logic Circuit Design Of Parallel Adders Using Resonant Tunneling Devices.
(Article)
Subject:
Adder
,
Arithmetic
Author:
C
Burwick
U
Auer
C
Pacha
page:
558
-
572
Interfacing Synchronous And Asynchronous Modules Within A High-Speed Pipeline.
(Article)
Subject:
Asynchronous Design
,
Low Control Overhead
Author:
C. J
Myers
A. E
Sjogren
page:
573
-
583
Improving The Efficiency Of Monte Carlo Power Estimation.
(Article)
Subject:
Monte Carlo Simulation
,
Very Large Scale Integration
Author:
C. S
Ding
C. T
Hsieh
M
Pedram
page:
584
-
593
A New Approach To Built-In Self-Testable Datapath Synthesis Based On Integer Linear Programming.
(Article)
Subject:
Built-In-Self-Test
,
Integer Linear Programming (Ilp)
Author:
T
Takahashi
H. B
Kim
D. S
Ha
page:
594
-
605
On The Measurement Of Crosstalk In Integrated Circuit.
(Article)
Subject:
Crosstalk
,
Rc Delay
Author:
E
Sicard
S
Delmass-Ben Dhia
F
Caignet
page:
606
-
609
Area-Time-Power Tradeoff In Cellular Arrays Vlsi Implementations.
(Article)
Subject:
Arithmetic
,
Complementary Metal-Oxide - Seimiconductor (Cmos)
Author:
G
Cocorullo
S
Perri
P
Corsonello
page:
614
-
623
Analysis Of Power Dissipation In Double Edge-Triggered Flip-Flops.
(Article)
Subject:
Complementary Metal-Oxide - Seimiconductor (Cmos)
,
Vlsi
Author:
C
Cimino
E
Napoli
page:
624
-
628
Cell-Based Layout Techniques Supporting Gate-Level Voltage Scaling For Low Power.
(Article)
Subject:
Layout
,
Voltage
Author:
Y. S
Kang
C
Yeh
page:
629
-
632
Deterministic Built-In Test Pattern Generation For High-Performance Circuits Using Twisted-Ring Counters.
(Article)
Subject:
Built-In-Self-Test (Bist)
,
Test Set Enbedding
Author:
V
Iyengar
B. T
Murray
K
Chakrabarty
page:
633
-
635
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